This invention relates generally to ultra-large-scale integration (ULSI) MOSFET integrated circuits. More particularly, it relates to a new and novel MOS transistor and a method of fabricating the same for ULSI systems which includes two assisted-gate electrodes to form ultra-shallow "pseudo" source/drain extensions.
As is generally known, in recent years advances made in the semiconductor process methodologies have dramatically decreased the device dimension sizes and have increased the circuit density on the IC chips. A MOSFET (metal-oxide-semiconductor field-effect transistor) device such as an N-channel MOS transistor or a P-channel MOS transistor has been used extensively for ultra-large-scale integration applications. Typically, the MOSFET devices are fabricated by patterning polysilicon gate electrodes over a thin gate oxide on a single crystal semiconductor substrate. The gate electrode is used as a diffusion or implant barrier mask to form self-aligned source/drain regions in the substrate adjacent to and on opposite sides of the gate electrode. The distance from the source region to the drain region under the gate electrode is defined as the "channel length" of the MOSFET device. Currently, the channel length dimension is less than 0.5 microns.
In order to increase the speed of the MOSFET devices, there has existed in the micro-electronics industry over the past two decades an aggressive scaling-down of the channel length dimensions. However, as the channel length reduction of the MOS transistor occurs, the source/drain extension junction depth must also be likewise aggressively reduced down in order to achieve acceptable immunity to the problem of "short-channel effects." One method of solving this short-channel effect problem is to form ultra-shallow extensions. Unfortunately, this method suffers from the drawback that it is very difficult to form such ultra-shallow extensions by using the conventional ion implantation technique. As a result, the problem of forming ultra-shallow extensions has become one of the major concerns for advanced deep-submicron MOSFET technology which limits its performance.
In view of the foregoing, there exists a need for MOS transistor and a method of fabricating the same for use in ULSI applications so as to provide ultra-shallow extensions without using the ion implantation process.